Sharp MZ-80B Owner's Manual page 131

122
A ROY
- -
v-
A STB
B ROY
B STB
Z-80A
KDATA BUS.)
Z-80A
CPU
I
ADDRESS BUS
IORQ
PIO
Ml
<
PORT DATA BUS
INT
BA C'D CE
"'""'~F-
BUS
DECODER
FIGURE 7.0-2
EXAMPLE 1/0 INTERFACE
D D D D
5 R R A
T 0
c
v
B
v
D
1 / 0
TERMINAL
Next, the proper interrupt vector is loaded (refer to CPU Manual for details on the operation of the interrupt).
Do
0
Interrupts are then enabled by the rising edge of the first M 1 after the interrupt mode word is set unless that M 1 defines
an interrupt acknowledge cycle. If a mask follows the interrupt mode word, interrupts are enabled by the rising edge of
the first M 1 following the setting of the mask.
Data can now be transferred between the peripheral and the CPU. The timing for this transfer is as described in
Section 5.0.