Sharp MZ-80B Owner's Manual page 119

110
The 2-bit mode control register is loaded by the CPU to select the desired operating mode (byte output, byte
input, byte bidirectional bus, or bit control mode) . All data transfer between the peripheral device and the CPU is
achieved through the data input and data output registers. Data may be written into the output register by the CPU or
read back to the CPU from the input register at any time . The handshake lines associated with each port are used to
control the data transfer between the PIO and the peripheral device.
The 8-bit mask register and the 8-bit input/output select register are used only in the bit control mode . In this
mode any of the 8 peripheral data or control bus pins can be programmed to be an input or an output as specified by
the select register. The mask register is used in this mode in conjunction with a special interrupt feature. This feature
allows an interrupt to be generated when any or all of the unmasked pins reach a specified state (either high or low).
The 2-bit mask control register specifies the active state desired (high or low) and if the interrupt should be generated
when
all
unmasked pins are active (AND CPU status checking of the peripheral by allowing an interrupt to be automat-
ically generated on specific peripheral status conditions. For example, in a system with 3 alarm conditions, an interrupt
may be generated if any one occurs or if all three occur.
The interrupt control logic section handles all CPU interrupt protocol for nested priority interrupt structures. The
priority of any device is determined by its physical location in a daisy chain configuration. Two lines are provided in
each PIO to form this daisy chain. The device closest to the CPU has the highest priority. Within a PIO, Port A inter-
rupts have higher priority than those of Port B. In the byte input, byte output or bidirectional modes , an interrupt can
be generated whenever a new byte transfer is requested by the peripheral. In the bit control mode an interrupt can be
generated when the peripheral status matches a programmed value. The PIO provides for complete control of nested
interrupts. That is , lower priority devices may not interrupt higher priority devices that have not had their interrupt
service routine completed by the CPU. Higher priority devices may interrupt the servicing of lower priority devices.
When an interrupt is accepted by the CPU in mode 2, the interrupting device must provide an 8-bit interrupt vector
for the CPU. This vector is used to form a pointer to a location in the computer memory where the address of the inter-
rupt service routine is located . The 8-bit vector from the interrupting device forms the least significant 8 bits of the
indirect pointer while the I Register in the CPU provides the most significant 8 bits of the pointer. Each port (A and B)
has an independent interrupt vector. The least significant bit of the vector is automatically set to a 0 within the PIO
since the pointer must point to two adjacent memory locations for a complete 16-bit address.
The PIO decodes the RETI (Return from interrupt) instruction directly from the CPU data bus so that each PIO
in the system knows at all times whether it is being serviced by the CPU interrupt service routine without any other
communication with the CPU.