Sharp MZ-80B Owner's Manual page 82

73
2.0
PIN DESCRIPTION
The Z-80A CPU is packaged in an industry standard 40 pin Dual In-Line Package. The 1/0 pins are shown in Figure
2.0-1 and the function of each is described below.
Ao-Ais
(Address Bus)
Do-D7
(Data Bus)
MI
27
30
A o
31
AI
MREQ
19 32
20
33
A2
SYSTEM IORQ
21
34
A3
CONTROL RD
35
A4
WR
22
36
A5
A6
28
37
38
A7
ADDRESS
As
BUS
HALT
18
39·
40
Ag
A 10
24
I
A11
CPU
2
A 12
CONTROL INT
16
3
Z-80A-CPU
4
A13
NMI
RESET
CPU {BUSRQ
BUS - -
CONTROL BUSAK
<I>
+5V
GND
17
26
25
23
6
II
29
Z-SOA PIN CONFIGURATION
FIGURE 2.0-1
A14
5
A1 5
14
15
12
8
Do
D,
D2
7
9
10
13
D3
DATA
D4
BUS
D5
D6
D 7
Tri-state output, active high. A
0
-A
15
constitute a 16-bit address bus. The address bus pro-
vides the address for memory (up to 64K bytes) data exchanger and for 1/0 device data
exchanges. 1/0 addressing uses the 8 lower address bits to allow the user to directly select
up to 256 input or 256 output ports . A
0
is the least significant address bit. During refresh
time, the lower 7 bits contain a valid refresh address.
Tri-state input/output, active high. D
0
-D
7
constitute an 8-bit bidirectional data bus. The
data bus is used for data exchanges with memory and 1/0 devices.
(Machine Cycle one)
Output, active low. M
1
indicates that the current machine cycle is the OP code fetch cycle
of an instruction execution. Note that during execution of 2-byte op-codes, M
1
is generated
as each op code byte is fetched. These two byte op-codes always begin with CBH, DDH,
EDH or FDH. M
1
also occurs with IORQ to indicate an interrupt acknowledge cycle.
MREQ
(Memory Request)
Tri-state output, active low. The memory request signal indicates that the address bus holds
a valid address for a memory read or memory write operation.