Sharp MZ-80B Owner's Manual page 113

104
P/
Instruction
c z v s
N
ADD A, s; ADC A,
s
t t
v
t
0
SUBs; SBC A, s, CPs, NEG
t
v
t
AND s
0
t
p
t
0
OR s;XORs 0
t
p
t
0
INC s
•
t
v
0
DECm
• v
t
1
ADD DD, ss
t
•
• •
0
ADC HL, ss
t t
v
0
SBC HL, ss
t t
v
1
RLA;RLCA,RRA,RRCA
t
•
• •
0
RL m ; RLC m ; RR m; RRC m
t t
p
0
SLAm ; SRA m ; SRL m
RLD,RRD
• p
t
0
DAA
p
t
•
CPL
• •
•
•
1
SCF
1
• • •
0
CCF
t
•
•
•
0
IN r, (C)
•
t
p
t
0
INI ; IND ; OUT!; OUTD
•
t
X X
INIR; INDR; OTIR; OTDR
•
1 X X 1
LDI, LDD
•
X t X
0
LDIR, LDDR
•
X 0 X 0
CPI, CPIR, CPD, CPDR
•
t
X
LD A, I; LD A, R
•
FF
0
BIT b, s
•
t
X X 0
NEG
t
v
The following notation is used in this table :
H
t
1
0
t
X
X
X
0
0
0
1
0
X
0
X
X
0
0
X
0
t
Comments
8-bit add or add with carry
8-bit subtract, subtract with carry, compare and negate accumulator
}
Logical operations
And set's different flags
8-bit increment
8-bit decrement
16-bit add
16-bit add with carry
16-bit subtract with carry
Rotate accumulator
Rotate and shift location s
Rotate digit left and right
Decimal adjust accumulator
Complement accumulator
Set carry
Complement carry
Input register indirect
}
Block input and output
Z = 0 if B
1
0 otherwise Z = 1
}
·Block transfer instructions
P/V
=
1 if BC
1
0, otherwise P/V
=
0
Block search instructions
Z = 1 if A = (HL), otherwise Z = 0
P/V
=
1 if BC
1
0, otherwise P/V
=
0
The content of the interrupt enable flip-flop (IFF) is copied into the
P/V flag
The state of bit b of locations is copied into th e Z flag
Negative accumulator
Symbol Operation
C Carry/link flag. C = 1 if the operation produced a carry from the MSB of the operand or resu lt.
Z Zero flag. Z
=
1 if the result of the operation is zero.
S Sign flag. S
=
1 if the MSB of the result is one.
P/V Parity or overflow flag. Parity (P) and overflow (V) share the same flag. Logical operations affect this flag with the parity
of the result while arithmetic operations affect this flag with the overflow of the result. If P/V holds parity, P/V
=
1 if the
resu lt of the operation is even, P/V
=
0 if result is odd. If P/V holds overflow, P/V
=
1 if the result of the operation produced
an overflow.
H Half-carry flag. H = 1 if the add or subtract operation produced a carry into or borrow from into bit 4 of the accumulator.
N Add/Su btract flag. N
=
1 if the previous operation was a subtract.
Hand N flags are used in conjunction with the decimal adjust instruction (DAA) to properly correct the result into packed
BCD format foll owing addition or su btraction using operands with packed BCD format.
The flag is affected according to the result of the operation.
• The flag is unchanged by the operation.
0 The flag is reset by the operation.
1 The flag is set by the operation.
X The flag is a "don't care."
V P /V flag affected according to the overflow result of the operation.
P P /V fl ag affected according to the parity result of the operation.
Any one of the CPU registers A, B, C, D, E, H, L.
Any 8-bit locatio n for all the addressing modes allowed for the particular instruction.
ss Any 16-bit location for all the addressing modes allowed for that instruction.
ii
Any o ne of the two index registers IX or IY.
R Refresh counter.
n 8-bit value in range <0, 255 >
nn 16-bit value in range < 0, 65535 >
m Any 8-bit location for all the addressing modes allowed for the particular instruction.
SUMMARY OF FLAG OPERATION
TABLE 4.4-1