REV.A
DREN
DAKN
FDAN
BTC
FTC
FDRQ
DRQ
FWD
WB
PSI
PSü
WD
C48
TEST
MIN
OSC
CLK
WCLK
PINT
SYNC
VDRQ
SIDE
HS
INV
INVN
SEEK
DTKO
TRKO
o
I
o
I
o
I
o
I
I
I
I
o
I
I
o
o
o
o
I
I
o
I
o
I
o
I
I
o
60
12
50
13
42
40
61
35
36
33
34
28
55
38
48
57
54
56
41
43
53
51
22
20
21
37
31
39
DIAGRAMS AND REFERENCE MATERIALS
(-) Enable DMA and interrupt.
(-)
D~~
acknowledge. (input frorn 8237)
(-) DMA acknowledge. (output to 765)
(+)
Terminal count. (input frorn 8237)
(+)
Terminal count. (output to 765)
(+)
D~~
request. (input from 765)
(+)
D}~
request. (output to 8237)
(+)
Write data. (input from 765)
(+)
Write enable. (input from 765)
Peak shift. (input from 765)
Peak shift. (input from 765)
(+)
Write data. (output to FDD)
48 MHz clock input.
(-) Test pin.
Mini/Standard. (for SED9420)
16/9.6 MHz clock output. (for SED9420)
FDC dock. (8/4.8/4
~rnz)
FDC write clock. (IM/600K/500K Hz)
(+)
Interrupt request of FDC. (input frorn 765)
VFO synchronize. (input frorn 765)
(+)
VFO DREQ. (for SED9420)
(+)
Side select. (Head select, input frorn 765)
(+)
Head select. (output to FDD)
Input of inverter.
Output of inverter.
(+)
Seek. (input from 765)
(+)
Track O. (input from FDD)
(+)
Track O. (output to 765)
*
Legend:
I
=
Input P in
o
Output P in
7-27