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REV.A
7.2.8
GAATRF
DIAGRAMS AND REFERENCE MATERIALS
GAATRF includes the following functional blocks.
1. DRAM refresh control circuit.
2. DHA control circuit.
3. 16
<-->
8 data conversion circuit.
4.
Wait states insertion circuit.
5. Command delay control circuit.
6. XAO, XBHE control circuit.
TABLE 7-2-12.
GAATRF PIN DESCRIPTION
SYMBOL
~.,rSO
WS1
1/0*
PIN NO.
I
15
I
40
NAME AND FUNCTION
Zero wait insertion. When low, wait state is not
inserted.
-OWS
signal
of
option
slot
is
connected to this pin.
Wait states control of BIOS-ROM access.
The number of wait states of BIOS-ROM (OEOOOO-
OFFFFF, FEOOOO-FFFFFF) is controlled by WS1.
CSPD
WS1
Wait states
0 (10
MHz)
0
2
0 (10
HHz)
1
1
1 (6 or
8
MHz)
*
1
(* :
don' t care)
WS2
I
39
WaU states control of 16-bit memory devices on
the option card which activates -MEMCS16 signal.
WS3
I
38
CSPD
~VS3
WS2
Wait states
0 (10
~mz)
0
0
4
0 (10
MHz)
0
1
3
0 (10
MHz)
1
0
2
0
(10 MHz)
1
1
1
1 (6 or
8
MHz)
*
*
1
(*
don't care)
AO
ALE
MEMR
MEMW
IOR
IOW
INTA
CSRA
CSRO
M16
I
44
I
11
I
7
I
8
I
9
I
10
I
12
I
48
I
47
I
17
CPU
address bus O.
(+)
Address latch enables.
(-) System memory read signal.
(-) System memory write signal.
(-) System 1/0 read signal.
(-) System 1/0 write signal.
(-) Interrupt acknowledge.
(-) Chip select
signal of internal DRAM (0-
09FFFF) •
(-) Chip select signal of internal ROM (OEOOOO--
-OFFFFF, FEOOOO-FFFFFF).
(-) Chip select signal of 16-bit memory devices
on the option siot. (-MEMCS16 signal of option
siot is connected to this pin.)
7-21
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