Epson PC AX Technical Manual page 189

REV .A DIAGRAMS AND REFERENCE MATERIALS
7.2.5
GAA'l'M2
GAATM2 generates memory address and RAS, CAS, WE signals used witb GAATM1 and
tbe delay line to control DRAM.
TADLE
7-2-9.
GAA'l'M2
PIN DESCRIPTION
SYMBOL
SA18-0
MA8-0
HEMR
HEMW
EMRN
XMWN
RFHN
D40
D80
D160
D200
RA1
RAO
CAR
CAL
RAS1
RAS0
CASH
CASL
WE
RAS
TEST
1/0*
I
o
I
I
I
I
I
I
I
I
I
I
I
I
I
o
o
o
o
o
o
I
PIX NO.
3,5,6,13-16,
18,20-24,
27-32
44,43,41,40,
9-7 ,12,11
61
62
46
63
64
52
50
48
47
35
37
38
39
59
60
56
55
45
53
54
NAME AND FUNCTION
System address bus.
DRAM address bus.
(-) System memory read signal.
(-) System memory write signal.
(-) Early memory read signal.
(-) Internal memory write signal.
(-) Refresb signal.
40 ns delayed signal from RAS.
80 ns delayed signal from RAS.
160 ns delayed signal from RAS.
200 ns delayed signal from RAS.
(+)
RA1 signal is used to generate RAS1 signal.
(+)
RAO signal is used to generate RASO signal.
(+)
CAR signal is used to generate CASH signal.
(+)
CAL signal is used to generate CASL signal.
(-) Row address strobe for DRAM (80000H-9FFFFH).
(-) Row address strobe for DRAM (OH-7FFFFH)
(-) Column address strobe for DRAM (OH-9FFFFH,
odd byte).
(-) Column address strobe for DRAM (OH-9FFFFH,
even byte).
(-) Write enable signal for DRAM.
(+)
RAS is generated from logical OR of MEMR and
HEMW. This output is used to generate delay
signals (D40, D80, D160, D200)
(-) Test input. TEST should be pulled up.
*
Legend:
I
=
Input Pin
o
Ouput Pin
7-15