Epson PC AX Technical Manual page 200

DIAGRAMS AND REFERENCE MATERIALS
7 .2 .10
GAATFD
GMTFD includes the following functional blocks.
1. Address decoder for FDC(765) and 1/0 registers.
2. 1/0 register.
FDOR : Floppy digital output register.
FCR : Floppy control register.
3. Write precompensation circuit.
4. Clock ci.rcuit
5. DMA request circuit.
TABLE 7-2-14. GAATFD PIK DESCRIPTIOK
REV.A
SYMBOL
1/0* PIK 1«>.
BA9-0
I
8-2,64-62
BD5-0
I
14-19
IOWN I
11
IORN I 10
AEN I 9
RSE
I
52
FDIl
I 46
FDIO
I 45
NAME AND FUNCTION
Address bus.
Data bus.
(-) 1/0 write pulse.
(-) 1/0 read pulse.
(+)
Address enable. This signal becomes high,
when DMA cycle is being executed.
(+) Reset.
Address select pin for FDC.
Address select pin for FDC.
FDIl FDIO FDC address AT/XT
1 1 3FO
3F7 AT portI
1
0
370 377
AT port2
0
1 3FO 3F7 XT
0
0 disable
(When FDll, FDIO = 0, 1 Floppy control register
can not be accessed.)
MOT2
MOTI
DS2
DSI
FRES
RlvC
3X7N
3XVN
FCSN
BDIR
7-26
o
o
o
o
o
o
o
o
o
o
30
29
25
24
49
23
32
47
44
59
(+) Motor enable 2. (DRIVE
B)
(+)
Motor enable 1. (DRIVE A)
(+) Drive select 2. (DRIVE B)
(+) Drive select 1. (DRIVE
A)
(+) FDC (765) reset signal.
(+) Reduced write current.
(-) Read 3X7 signal. This signal becomes active
while 1/0 address 3X7 is read. X means F (when
FDIO=I) or 7 (when FDIO=O)
(-) Chip select of 3X6 and 3X7. This signal
becomes active while 1/0 address 3X6 or 3X7 are
accessed.
(-) Chip select of FDC (765).
(~) Direction control of data buffer. This
signal is active whiJe FDC (765) is being read.
(CPU access or DMA transfer)