Epson PC AX Technical Manual page 186

DIAGRAMS AND REFERENCE MATERIALS
7.2.4
GAATCK
GAATCK includes following functional blocks.
(1)
Clock generator
CPU dock, 80287 dock, System clock,
DMA clock,
8042 dock, 8254 dock,
NTSC dock (14.31818 MHz)
(2) Ready circuit
(3) Reset circuit
(4) Bus controller
HEMR, MEMW, lOR, lOW, lNTA, ALE, DTR, DEN
(5) Shut down circuit
TABLE 7-2-7. GAATCK PIR ARRANGEMENT
SIGNAL PIR PIR
SIGNAL
NAME
1/0*
JIiI) • JIiI) •
1/0*
NAME
,
..•
_,_
..
_ ~ - - _ . ~ . _ - - , .
-----.
--._.-.~.,,---
..
----.----
..
_._.-
C14M I 1 64 Vcc
HLDA
I
2
63 I C48H
Al
I
3 62 I COFF
RSWN I 4
61 I CDLY
RSWP
I
5 60
I
CSPDO
PWGD I 6 59
I
CSPD1
(NC) 7 58 (NC)
(NC) 8 57 (NC)
(NC) 9
56
0 RSN
ENAS 0 10 55 0 C1M
DTR 0
11
54 0 EMEMR
ACKN 0 12 53 0 DEN
EALE
0
13
52 0 BALE
RSDV 0 14 51 0 AEN
CLKO
0
15
50 0 SCLK
GNDA 16 49 GNDB
GNDB 17 48 GNDA
MEHR O&lI-Z 18 47
0 OSC
MEMW O&H-Z 19 46 O&H-Z lOR
ALE
0
20 45 O&lI-Z IOW
lNTA O&H-Z 21 44 0 PCLKP
DCLK 0 22
43
0 PCLKN
RDY 0 23 42 0 RSCPU
(NC) 24 41 0 C8H
(NC) 25 40 (NC)
RC
I
26
39 (NC)
HSTR
I
27 38 (NC)
HlO
I 28 37
I
SRDY
Sl I 29 36 I ARDY
SO I 30 35
I
AREN
C20M I 31 34 I TEST
Vcc 32 33 I CLKI
*
Legend: I Input Pin
0
=
Output Pin
O&H-Z Output & High-impedance P in
7-12
REV.A