Epson PC AX Technical Manual page 180

DIAGRAMS AND REFERENCE MATERIALS
REV.A
7.2 GATE ARRAY DESCRIP TION
7.2.1 GAATAB
GAATAB controls the CPU address bus, system address bus and the internal
address bus.
I t
has an 8-bit refresh counter.
TABLE 7-2-1.
GAATAB P IN ARRANGEMENT
SIGNAL PIN
PIK
SIGNAL
NAME
1/0*
NO.
NO. 1/0* NAME
TESTN
I 1 64 Vcc
ALP. I 2 63 I A16
Al I 3 62 I Al5
AZ I 4 61
I
A14
A3 I
5 60 I
Al3
XAO Tri
6 59 Tri XA16
XAl Tri
7 58 Tri XA15
LSAO I 8
57
T
DXA
XAZ Tri
9 56
Tri XA14
XA3 Tri 10 55 Tri XA13
SAO Tri
11 54
Tri. XA12
SA1
Tri 12
53
Tri SA16
SA2 Tri 13 52 Tri SA15
SA3 Tri 14
51
Tri SA14
SM Tri.
15 50 Tri SAl3
GNDA 16 49 GNDB
GNDB 17
48
GNDA
SAS
Tri
18 47
Tri
SA12
SA6
Tri
19 46 Tri SAH
SA7 Tri 20 45 Tri SA10
SA8 Tri 21 44 Tri SA9
XA4 Tri
22 43
Tri XAll
XAS Tri 23 42 Tri XA10
XA6 Tri
24 41
Tri XA9
OP.-N I 25 40 I R590N
XA7 Tri 26
39
Tri XA8
A4
I 27 38 I A12
A5 I 28 37 I All
A6 I 29
36 I
A10
A7
I 30 35 I A9
A8
J
31 34 I G590N
Vcc
32 33
I
C590
*
Legend: I Input P in
0 Output P in
Tri Tri-state Pin (Input, Output, High-impedance)
7-6