Epson PC AX Technical Manual page 197

REV.A
OUT1
HRQ1
XHW
HRQ
HLDA
HAK1
RFNO
RFNI
RFPO
RFlD
RF2D
DMMR
XIOR
DRDY
XMR
CA20
A20G
A20
I
I
I
o
I
o
o
I
o
o
o
I
I
o
O&H-Z
I
I
O&H-Z
21
22
46
30
3
31
28
63
24
37
36
41
50
29
64
34
33
62
DIAGRAMS AND REFERENCE MATERIALS
OUT1 signal of 8254 (Timer LSI)
(+)
Hold request input from 8237
(D}~C
LSI).
(-) Internal memory write signal.
(+)
Hold request output to CPU.
(+)
Hold acknowledge input from CPU.
(+)
Hold acknowledge output to 8237 (DMAC LSI).
(-) Refresh signal. This signal is generated in
GAATRF.
(-) Refresh signal input.
(+)
Refresh signal.
(-) Refresh signal which is delayed by one DMA
clock cyc1e from RFNI signal.
(-) Refresh signal which is delayed by two DMA
clock cycles from RFNI signal.
(-)
D}~
memory read signal.
(-) Internal 1/0 read signal.
(+)
D~~ ready signal.
(-) Internal memory read signal.
CPU address bus 20. A20 signal of CPU is
connected to this pin.
(+)
Gate signal of A20. P21 signal of 8042 (one
chip CPU) is connected to this pin.
System address bus 20.
CA20
o
1
*
A20G
1
1
o
A20
o
1
o
(*
don' t care)
CLK
SCLK
DCLK
I
I
I
51
6
13
Processor clock.
System clock.
DMA c1ock.
CPU speed
6 HHz
8 ~rnz
10 MHz
CLK
12 HHz
16 MHz
20 MHz
SCLK
6
HHz
8
MHz
10
}ffiz
DCLK
3 MHz
4
tffiz
5 HHz
RST
RSTO
TEST
I
o
I
20
19
53
(-) Reset input.
(+)
Reset output.
(-) Test input.
*
Legend: I
o
Tri
O&H-Z
Input Pin
Output P in
Tri-state Pin (Input, Output, High-impedance)
Output
&
High-impedance P in
7-23