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DIAGRAHS AHn REFERENCE MATERIALS
REV.A
COFF
CDLY
HLDA
ALE
DEN
DTR
MEHR
MEMW
IOR
IO\-l
INTA
EHEHR
EALE
BALE
MSTR
ACKN
AEN
Al
Re
RSCPU
ENAS
TEST
1
1
1
I
I
I
o
o
o
O&H-Z
O&H-Z
O&H-Z
O&H-Z
O&Il-Z
o
o
o
I
o
o
I
I
o
o
I
o
1
1
62
61
2
20
53
11
18
19
46
45
21
54
13
52
27
12
51
3
26
42
10
34
1
o
1
MEHORY READ
MEMORY WRI TE
NONE, IDLE
(+)
Control off. When high,
command and DEN
signal are forced inactive.
Command delay. When high, the start of command
output is delayed.
Hold acknowledge. When high,
command output
becomes 3-state off.
Address latch enable.
Data bus enable.
Data transmit/receive. "!hen high, this control
output indicates that a write bus cycle is being
performed.
(-) Hemory read command.
(-) Hemory write command.
(-) 1/0 read command.
(-) 1/0 write command.
(-) Interrrupt acknowledge.
(-) Early memory read signal.
Early address latch enable.
Buffered address latch enable.
(-) Haster. A processor or DHA controller on the
1/0 channel may pull this signal low.
(-) Acknowledge. \l.Then low,
mtA
controller (or
refresh controller) has control of the address
bus, data bus and control bus.
(+)
Address enable.
Address 1.
(-) Reset CPU input from 8042.
(+)
Reset CPU output. When high, CPU is reset.
RSCPU becomes active when:
(1)
P~?GD
is low·.
(2) Reset switch is activated.
(3) 8042 pulls RC signal low.
(4) CPU executes shutdown cycle.
(-) Enable control of RTCAS (RTC address strobe)
signal.
(-) Test input. TEST should be pulled high.
7-14
*
Legend:
0
I
O&H-Z
Output
Input
Output & High-impedance Pin
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