Epson PC AX Technical Manual page 191

REV.A
ITAN
SMIO
NERN
NBSN
Q1
ENAS
CD2N
CD1N
CI2N
CIlN
CTMN
CKBN
RTRW
RTDS
RTAS
NPRS
NCSN
CBSN
IR13
DXD
NMI
SPEK
TM2G
ENPR
IOEN
OUT2
PCKN
VI
VO
NA
II
NAZI
NAnO
TS20
TSI
TSO
TSVI
TSVO
I
I
I
I
I
I
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
I
I
I
o
I
I
o
O&II-Z
I
O&H-Z
I
O&H-Z
100
88
8
7
89
98
24
25
42
41
47
99
44
45
46
6
5
9
43
39
10
51
48
81
92
49
82
84
83
95
94
93
91
1
2
13
50
DIAGRAMS AND REFERENCE MATERIALS
-INTA. Interrupt acknowledge.
Memory or 1/0 select.
(-) NP
(80287) error.
(-) NP
(80287) busy.
Q1 is a timing signal to generate RTAS signal.
(-) Enable control ot RTAS signal.
(-) Chip select of D~~C2 (8237).
(-) Chip select of DMAC1 (8237).
(-) Chip select of INTC2 (8259).
(-) Chip select of INTC1 (8259).
(-) Chip select of system TIMER (8254).
(-) Chip select of keyboard controller (8042).
(-) Write signal of real time clock (HD146818).
(-) Read signal of RTC (HD146818)
(+)
ALE signal of RTC (HD146818).
(+)
NP
(80287) reset signal.
(-) Chip select ~w
(80287).
(-) CPU (80286) busy signal.
(+)
Interrupt request 13.
Direction control of
8
bit internal data bus
(XD7-0) buffer.
(+)
Non-maskable interrupt request.
Output signal for speaker.
Time r CH2 gate. This signal is connected to
channel 2 gate input of timer LSI (8254).
(+)
Enable
RAM
parity check.
1/0 channel error (option slot).
Timer CH2 output. This signal is connected to
channel 2 output of timer LSI (8254).
(-) Parity check error.
Input of inverter.
Output of inverter.
Input of NAND gate.
Input of NAND gate.
Output of NAND gate.
Output of 3-state buffer.
Enable control (active low) of 3-state buffer.
Output of 3-state buffer.
Enable control (active low) of 3-state buffer.
Output of 3-state buffer.
*
Legend: I
o
Tri
O&l1-Z
Input P in
Ouput Pin
Tri-state Pin (Input, Output, High-impedance)
Output
&
High-impedance P in
7-17