Bga Escape Example; Hm-Zd Design Example - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 14: Guidelines and Examples
transceivers have a die capacitance of 500 fF to 600 fF, most transitions can be designed to
have a very small impact on performance up to speeds of 10 Gb/s.
These guidelines are recommended to be followed even for designs slower than 10 Gb/s,
allowing for more margin at lower speeds such that a smaller output signal swing can be
used. Having a 10 Gb/s capable channel also provides the option to upgrade the
bandwidth of the system for the next generation product.

BGA Escape Example

The transceiver signal pairs are routed along the edges of the flip-chip BGA. A microstrip
is used to escape. When there is adequate spacing from the BGA, the optimized GSSG
differential vias are used to change layers, if needed. It is recommended that these vias be
staggered, as shown in
ground planes.
The round BGA pads for the transceiver signals present a small amount of capacitance to
a solid PCB ground below. Therefore one consideration is to open a void in the ground
plane below the signal pads with the same diameter as the signal pads. However,
simulations show that the void only removes 30 fF of capacitance.

HM-Zd Design Example

For backplane applications, in-line connectors such as the one shown in
most common. Of these connectors, the most common mounting method is press-fit,
although SMT connectors offer much better performance.
252
Figure 14-1, to minimize the formation of slots in the power and
Figure 14-1: BGA Escape Design Example
www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196_c14_01_051406
Figure 14-2, are the
UG196 (v1.3) May 25, 2007
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