Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 8: Cyclic Redundancy Check (CRC)
The CRC block only calculates the CRC for the input datastream using the standard
polynomial. The CRC blocks do not perform any data framing. The application is
responsible for appending CRC values to outgoing frames and validating the CRC on the
RX side.

Ports and Attributes

Table 8-1
Table 8-1: CRC 64-Bit I/O Ports
Port
CRCCLK
CRCDATAVALIDA
CRCDATAWIDTH[2:0]
CRCIN[63:0]
CRCOUT[31:0] Out
CRCRESET
188
TX User
Data
CRC Residue
CRC Residue
RX User
Data
CRC Pass/Fail
defines the CRC 64-bit I/O ports, and
Port Clock
Dir
Size Domain
In 1 N/A CRC clock
Indicates valid data on the CRCIN inputs.
In 1 CRCCLK
Deasserting this signal causes the CRC value to be held for the
number of cycles that this signal is deasserted.
Indicates how many input data bytes are valid. Refer to
In 3 CRCCLK page 190
and CRC64, respectively.
In 64 CRCCLK CRC input data. The maximum datapath width is eight bytes.
32-bit CRC output. CRCOUT is the byte-reversed, bit-inverted CRC
value corresponding to the CRC calculation on valid bytes from the
32 CRCCLK
previous clock cycle and the previous CRC value. Note:
CRCDATAVALIDA must be driven High.
Synchronous reset of CRC registers. When CRCRESET is asserted,
In 1 CRCCLK
the CRC block is initialized to the CRC_INIT value.
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CRC Block
RX_CRC =
CRC Block
Figure 8-2: CRC Application
Table 8-2
Description
1'b1: Data valid
1'b0: Data invalid
and Table 8-5, page 190
Virtex-5 RocketIO GTP Transceiver User Guide
Transmitter
I/F
Receiver
I/F
UG196_c8_02_100506
defines the CRC 32-bit I/O ports.
Table 8-4,
for input byte ordering for CRC32
UG196 (v1.3) May 25, 2007
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