Extended Capabilities Port Mode; Parallel Interface Programming - HP dx7300 Technical Reference Manual

Input/Output Interfaces

5.5.3 Extended Capabilities Port Mode

The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based
design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as
well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode
includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or
programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is
entered to detect whether or not the connected peripheral is compatible with ECP mode. If
compatible, then ECP mode can be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO
is cleared and not used, and DMA and RLE are inhibited.

5.5.4 Parallel Interface Programming

Programming the parallel interface consists of configuration, which typically occurs during
POST, and control, which occurs during runtime.
Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and
also must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
SCH5317 I/O controller. Address selection and enabling are automatically done by the BIOS
during POST but can also be accomplished with the Setup utility and other software.
The parallel interface configuration registers are listed in the following table:
Parallel Interface Configuration Registers
Index
Address Function
30h Activate
60h Base Address MSB
61h Base Address LSB
70h Interrupt Select
74h DMA Channel Select
F0h Mode Register
F1h Mode Register 2
5-12
Table 5-10.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Reset Value
00h
00h
00h
00h
04h
00h
00h
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