HP dx7300 Technical Reference Manual page 57

The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration
space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of
configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space
header.
31 24 23
Min. Lat.
Ex pansion ROM Base Address
Subs ystem ID
Configuration
Space
Header
Base Address Registers
BIST
Class Code
Status
Device ID
PCI Configuration Space Type 0
Data required by PCI protocol
Figure 4-3. PCI Configuration Space Mapping
PCI 2.3 Bus Master Arbitration
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used
by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it's REQn signal to the PCI bus arbiter (a
function of the system controller component). If the bus is available, the arbiter asserts the GNTn
signal to the requesting device, which then asserts FRAME and conducts the address phase of the
transaction with a target. If the PCI device already owns the bus, a request is not needed and the
device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and
request signals assignments for the devices on the PCI bus.
Technical Reference Guide
16 15 8 7
Device-Specific Area
Min. GNT Int. Pin Int. Line
Reserved
Reserved
Subs ystem Vendor ID
Card Bus CIS Pointer
Hdr. T ype Lat. Timer Line Size
Revision ID
Command
Vendor ID
0 Index 31 24 23
FCh
40h
Brid ge Control
3Ch
Ex pansion ROM Base Address
38h
34h
I/O Limit Upper 16 Bits
30h
Prefetchable Limit U pper 32 Bits
2Ch
28h
Prefetchable Base U pper 32 Bits
Prefetch. Mem. Limit
Memory Limit
Secondar y Status
nd
2 Lat.Tmr
10h
BIST
0Ch
08h
04h
Status
00h
Device ID
PCI Configuration Space Type 1
Not required
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16 15 8 7
Device-Specific Area
Int. Pin Int. Line
Reserved
I/O Base U pper 16 Bits
Prefetch. Mem. Base
Memory Base
I/O Limit I/O Base
Sub. Bus # Sec. Bus # Pri. Bus #
Base Address Registers
Hdr. T ype Lat. Timer Line Size
Class Code Revision ID
Command
Vendor ID
Index
0
FCh
40h
3Ch
38h
34h
30h
2Ch
28h
24h
20h
1Ch
18h
10h
0Ch
08h
04h
00h
4-5