HP dx7300 Technical Reference Manual page 80

Input/Output Interfaces
SATA Configuration Registers
The SATA controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the SATA controller function (PCI device #31, function #2) are listed
in Table 5-1.
SATA PCI Configuration Registers (82801, Device 31/Function 2)
PCI Conf.
Addr.
00-01h
02-03h
04-05h
06-07h
08h
09h
0Ah
0Bh
0Dh
0Eh
SATA Bus Master Control Registers
The SATA interface can perform PCI bus master operations using the registers listed in Table
5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table. As indicated, these registers are virtually a copy
of those used by EIDE operations discussed in the EIDE section.
I/O Addr.
Offset
00h
02h
04h
08h
0Ah
0Ch
5-2
Register
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming
Sub-Class
Base Class Code
Master Latency Timer
Header Type
Table 5-2.
IDE Bus Master Control Registers
Size
(Bytes) Register
1 Bus Master IDE Command (Primary)
1 Bus Master IDE Status (Primary)
4 Bus Master IDE Descriptor Pointer (Primary)
1 Bus Master IDE Command (Secondary)
2 Bus Master IDE Status (Secondary)
4 Bus Master IDE Descriptor Pointer (Secondary
Table 5-1.
Reset PCI Conf.
Value Addr.
8086h 0F..1Fh
24D1h 10- 1 7h
0000h 18- 1 Fh
02B0h 20-23h
00h 2C, 2Dh
8Ah 2E, 2Fh
01h 34h
01h 3Ch
00h 3Dh
00h 40-57h
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Reset
Register Value
Reserved
Pri. Cmd, Cntrl. 1 (both)
Addrs.
Sec. Cmd, Cntrl. 1 (both)
Addrs.
BMstr Base Address
Subsystem Vender ID 0000h
Subsystem ID 0000h
Capabilities pointer 80h
Interrupt Line 00h
Interrupt Pin 01h
Timing, Control All 0's
Default Value
00h
00h
0000 0000h
00h
00h
0000 0000h
Technical Reference Guide
0's
1