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Motherboard Description
copies of each for electrical loading), enabling the support of up to
six 64-bit rows of SDRAM. The Intel® 815EP B-step MCH targets
SDRAM with CL2 and CL3 and supports both single and
double-sided DIMMs. Additionally, the Intel® 815EP B-step MCH
also provides a 1024 deep refresh queue. The Intel® 815EP B-step
MCH can be configured to keep up to 4 page op[en within the
memory array. Pages can be kept open in any one bank of memory.
SCKE[4:0] is used in configurations requiring powerdown mode for
the SDRAM.
1-6.5 AGP Interface
A single AGP connector is supported by the Intel® 815EP B-step
MCH AGP interface. The AGP buffers operate in one of two
selectable modes in one of two selectable modes in order to support
the AGP Universal Connector:
1) 3.3V drive, not 5 volt safe – This mode is compliant to the AGP
1.0 and 2.0 specs.
2) 1.5V drive, not 3.3 volt safe – This mode is compliant with the
AGP 2.0 spec.
The following table shows the AGP Data Rate and the Signaling
Levels supported by the MCH:
Data Rate
1x AGP
2x AGP
4x AGP
The AGP interface supports 4x AGP signaling. AGP semantic
(PIPE# or SBA[7:0]) cycles to SDRAM are not snooped on the host
bus. AGP FRAME# cycles to SDRAM are snooped on the host bus.
The MCH supports PIPE# or SBA[7:0] AGP address mechanisms,
but not both simultaneously. Either the PIPE# or the SBA[7:0]
mechanism must be selected during system initialization. High
priority accesses are supported. Only memory writes form the hub
Signaling Level
1.5V
3.3V
Yes
Yes
Yes
Yes
Yes
No
10
SY-TISU
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