Host Interface - SOYO SY-TISU User Manual

Motherboard Description

1-6.3 Host Interface

The host interface of the Intel® 815EP B-step MCH is optimized to
support the Intel® Pentium III processor and Intel® Celeron™
Processor in the FC-PGA package. The Intel® 815EP B-step MCH
implements the host address, control, and data bus interfaces within
a single device. The Intel® 815EP B-step MCH supports a 4-deep
in-order queue(i.e., supports pipelining of up to 4 outstanding
transaction requests on the host bus). Host bus addresses are
decoded by the Intel® 815EP B-step MCH for accesses to system
memory, PCI memory and PCI I/O (via hub interface), PCI
configuration space and Graphics memory. The Intel® 815EP B-step
MCH takes advantage of the pipelined addressing capability of the
pipelined addressing capability of the processor to improve the
overall system performance.
The Intel® 815EP B-step MCH supports the 370-pin socket
processor.
*370-pin socket (PGA370). The PGA370 is a zero insertion force
(ZIF) socket that a processor in the FC-PGA package will use to
interface with a system board.
1-6.4 System Memory Interface
The Intel® 815EP B-step MCH integrates a system memory
controller that supports a 64-bit 100/133 MHz SDRAM array. The
only DRAM type supported is industry standard Synchronous
DRAM (SDRAM). The SDRAM controller interface is fully
configurable through a set of control registers.
The Intel® 815EP B-step MCH supports industry standard 64-bit
wide DIMMs with SDRAM devices. The thirteen multiplexed
address lines. SMAA[12:0], along with the two bank select lines,
SBS[1:0], allow the Intel® 815EP B-step MCH to support 2M, 4M,
8M, 16M, and 42M x64 DIMM. Only asymmetric addressing is
supported. The Intel® 815EP B-step MCH has 6 SCS# lines (2
AGP 1X/2X/4X Controller
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