SOYO SY-TISU User Manual page 66

Fc-pga socket 370 processor supported 815ep universal agp/pci/cnr 66/100/133 mhz front side bus supported atx form factor
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BIOS Setup Utility
CHIPSET FEATURES SETUP(Continued)
CHIPSET
Setting
FEATURES
Disabled
CPU Latency
Timer
Enabled
Disabled
Delayed
Transaction Enabled
64MB
AGP
Graphics
32MB
Aperture
Size
Description
When enabled this item, the CPU
cycle will only be deferred after it has
been held in a "Snoop Stall" for 31
clocks and another ADS# has arrived.
When disabled, the CPU cycle will be
deferred immediately after the MCH
receives another ADS#.
The chipset has an embedded 32-bit
posted write buffer to support delay
transactions cycles. Select Enabled to
support compliance with PCI
specification version 2.1.
Select the size of Accelerated Graphics
Port (AGP) aperture. The aperture is a
portion of the PCI memory address
range dedicated for graphics memory
address space. Host cycles that hit
the aperture range are forwarded to the
AGP without any translation.
62
SY-TISU
Note
Default
Default
Default

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