Chipset - SOYO SY-TISU User Manual

Motherboard Description

1-6 CHIPSET

The Intel 815EP B-step universal platform contains a Memory
Controller Hub (MCH) component and I/O Controller Hub2 (ICH2)
component for desktop platforms.
The MCH provides the processor interface (optimized for the
Coppermine and Tualatin processors), DRAM interface, hub
interface, and an Accelerated Graphics Port (AGP) interface. This
product provides flexibility and scalability in graphics and memory
subsystem performance.
The Accelerated Hub Architecture interface (i.e., the chipset
component interconnect) is designed into the chipset to provide an
efficient, high-bandwidth communication channel between the Intel
815EP B-step universal platform's and memory controller hub and
the I/O controller hub. The chipset architecture also enables a
security and manageability infrastructure through the Firmware Hub
component.
An ACPI-compliant Intel 815EP B-step universal platform can
support the Full-on (S0), Stop Grant (S1), Suspend to RAM (S3),
Suspend to Disk (S4), and Soft-off (S5) power management states.
The chipset also supports wake-on-LAN for remote administration
and troubleshooting. The chipset architecture removes the
requirement for the ISA expansion bus that was traditionally
integrated into the I/O subsystem of PCIsets/ AGPsets. This removes
many of the conflicts experienced when installing hardware and
drivers into legacy ISA systems. The elimination of ISA provides
true plug-and-play for the platform. Traditionally, the ISA interface
was used for audio and modem devices. The addition of AC'97
allows the OEM to use software-configurable AC'97 audio and
modem coder/decoders (codecs), instead of the traditional ISA
devices.
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SY-TISU