Nvidia nForce4 4X User Manual page 34

For amd socket 754 based athlon 64 processor
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BIOS
Row cycle time (Trc)
This field specifies the Row Cycle Time. RAS# active to RAS# active or auto refresh
of the same bank.
Options: Auto, 7T ~ 21T.
Row refresh cyc time (Trfc)
This field specifies the Row Refresh Cycle Time. Auto-refresh active to RAS# or
RAS# to auto refresh.
Options: Auto, 9T ~ 23T.
Row to Row delay (Trrd)
This field specifies the Row to Row delay of different banks.
Options: Auto, 2T ~ 4T.
Write recovery time (Twr)
This bits specifies the Write Recovery Time. Called Trd1 by Samsung, measures
when the last write datum is safely registered by the DRAM. It measures from the
last data to precharge.
Options: Auto, 2, 3.
Write to Read delay (Twtr)
This bits specifies the Write to Read delay. Samsung Calls this Tcd1r (last data in to
read command). It is measured from the rising edge following the last non-masked
data strobe to the rising edge of the next Read Command. (Jedec spec this as exactly
one clock).
Options: Auto, 1, 2.
Read to Write delay (Trwt)
This field specifies the Read to write delay. This is not a DRAM specified timing
parameter but must be considered due to routing latencies on the clock forwarded
bus. It is counted from first address but slot which was not associated with part of
the read burst.
Options: Auto, 1 ~ 6.
Refresh Rate (Tref)
This field specifies the number of clock cycles between refresh.
Options: Auto, 15.6us, 7.8us, 3.9us.
DQS Skew Control
Options: Auto, Increase, Decrease.
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