Reset Methods; Reading The Present Value - Omron SYSMAC CJ Series User Manual

7 High-speed Counters
7-2-3

Reset Methods

Setting a high-speed counter's PV to 0 is called resetting.
There are two reset methods.
• Phase-Z Signal + Software Reset
• Software Reset
Phase-Z Signal + Software Reset
The high-speed counter's PV is reset when the phase-Z signal (reset input) turns ON while the corre-
sponding High-speed Counter Reset Bit (A531.00 to A531.03) is ON.
The CPU Unit recognizes the ON status of the High-speed Counter Reset Bit only at the beginning of
the PLC cycle during the overseeing processes. Consequently, when the Reset Bit is turned ON in the
ladder program, the phase-Z signal does not become effective until the next PLC cycle.
Phase Z
Reset bit
PV not
reset
Software Reset
The high-speed counter's PV is reset when the corresponding High-speed Counter Reset Bit (A531.00
to A531.03) turns ON.
The CPU Unit recognizes the OFF-to-ON transition of the High-speed Counter Reset Bit only at the
beginning of the PLC cycle during the overseeing processes. Reset processing is performed at the
same time. The OFF-to-ON transition will not be recognized if the Reset Bit turns OFF again within the
same cycle.
Reset Bit
Reset
Additional Information
The comparison operation can be set to stop or continue when a high-speed counter is reset.
This enables applications where the comparison operation can be restarted from a counter PV of
0 when the counter is reset.
7-2-4

Reading the Present Value

The present value of a high-speed counter can be read in the following three ways.
• Value refreshed at the I/O refresh timing
• Value updated when a ladder program is executed
• PV when an interrupt input occurs
7-16
One cycle
Reset Reset Reset
One cycle
Not reset Not reset Not reset
→
Not reset Reset
→
Read PV from Auxiliary Area.
→
Read PV by executing a PRV(881)
instruction.
Use the software latch and read the
value from the Auxiliary Area.
CJ2M CPU Unit Pulse I/O Module User's Manual