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4—SCC3 Tx Channel
5—SCC3 Rx Channel
Next, the pointer that caused the bus error can be determined by reading the Rx or Tx inter-
nal data pointer from the parameter's memory map of the particular SCC. Following this bus
error, the CP must be reset with a hardware reset or the setting of the RST bit in the com-
mand register.
An SDMA retry cycle is not indicated with any status information or interrupts.
4.5.9 SCC Transparent Mode
The SCC supports several transparent receive and transmit modes, which vary according
to the protocol being implemented. As used here, transparent means data transparency and
is not the same as the totally transparent (promiscuous) mode described later in 4.5.16
Transparent Controller. The transparent modes for each protocol are as follows:
UART Mode
If the normal mode is selected (UM1–UM0 = 00 in the UART mode register) and the con-
trol characters table is empty, then the UART will transfer all received characters to mem-
ory except break and idle characters.
HDLC Mode
When the HDLC mask register = $0000, the HDLC controller will transfer all received
frames to the receive buffers, including address, control, data, and CRC. The HDLC con-
troller still performs the standard HDLC functions of zero insertion/deletion and flag rec-
ognition.
BISYNC Mode
The BISYNC mode may be used to transparently receive data that is delimited by SYNCs.
To do this, the BISYNC control characters table should be empty, and SYNC/DLE strip-
ping should be disabled. Thereafter, all data following the SYNCs will be received into the
receive buffers.
There are two possible ways of recognizing SYNCs. Either the EXSYN bit in the BISYNC
mode register is cleared and a SYNC is defined by the SYN1–SYN2 characters in DSR, or
the EXSYN bit is set and a SYNC is determined by an external SYNC pulse.
When the BISYNC control characters table is empty, the SYNC and DLE stripping is dis-
abled, and the BISYNC controller is in normal nontransparent mode (RTR = 0 in BISYNC
mode register). In this case, the configuration is as follows:
• If EXSYN in the BISYNC mode register is cleared, then the BISYNC controller transfers
all characters that follow the SYN1–SYN2 sequence to the receive buffers.
• If EXSYN in the BISYNC mode register is set, then the BISYNC controller transfers all
characters that follow the external SYNC pulse to the receive buffers.
The BISYNC controller can reverse the bit order in both modes.
MOTOROLA
NOTE
MC68302 USER'S MANUAL
Communications Processor (CP)
4-41
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