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reduce power. An external pullup should be used if TCLK1 is not driven externally.
TSTCLK1 may be toggled at any time, but the SCC1 transmitter should be disabled
and re-enabled if any dynamic change is made on TSTCLK1 during the operation
of the SCC1 transmitter.
TSRCLK1—Three-state RCLK1
0 = Normal operation
1 = The RCLK1 pin is three-stated. This option may be used to prevent contention on
the RCLK1 pin if an external clock is provided to the RCLK1 pin while the SCC1
baud rate generator is output on RCLK1. This option may also be chosen if it is re-
quired to run the SCC1 baud rate generator at high speed (for instance in a high
speed UART application), but the RCLK1 output is not needed, and it is desired to
reduce power. An external pullup should be used if RCLK1 is not driven externally.
TSRCLK1 may be toggled at any time, but the SCC1 receiver should be disabled
and re-enabled if any dynamic change is made on TSRCLK1 during the operation
of the SCC1 receiver.
DBRG1—Disable BRG1
0 = Normal operation
1= The BRG1 pin is disabled and is driven high. This option should be chosen if it is
required to run the SCC1 baud rate generator at high speed, but the BRG1 output
is not needed and it is desired to reduce power. Although DBRG1 may be modified
at any time, the user should note that glitches on BRG1 are not prevented by the
MC68302 when the state of DBRG1 is changed.
Bits 10 - 0—Reserved. Should be written with zeros.
3.9.1 Freeze Control
Used to freeze the activity of selected peripherals, FRZ is useful for system debugging pur-
poses. When FRZ is asserted:
• The CP main controller freezes its activity on the next clock (CLKO) and will continue
in a frozen state as long as FRZ remains asserted. No new interrupt requests and no
memory accesses (internal or external) will occur, and the main controller will not ac-
cess the serial channels.
• The IDMA completes any bus cycle that is in progress (after DTACK is asserted) and
releases bus ownership. No further bus cycles will be started as long as FRZ remains
asserted.
• Each timer can be programmed to freeze by setting the appropriate bit in the SCR. After
a one-clock (CLKO) delay, the selected timers will freeze their activity (count, capture)
as long as FRZ remains asserted.
Regardless of whether or not the freeze logic is used, FRZ must
be negated during system reset.
MOTOROLA
NOTE
MC68302 USER'S MANUAL
System Integration Block (SIB)
3-65
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