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Table 5-11. PM3 Interconnect Signals (Continued)
PIN
MOTHERBOARD
SIGNAL
85
PA1
86
GND
87
88
—
89
PA0
90
GND
91
92
TMS
93
PB16
94
TRST
95
PB15
96
RS_EN1
97
PB14
98
PC4
99
PC5
100
PC6
101
GND
102
RS_EN2
103
SHIFT_C
104
GND
105
106
HSYNC
107
VSYNC
MOTOROLA
DAUGHTERBOARD
INPUT/
SIGNAL
OUTPUT
PA1
GND
—
PA0
GND
TMS
PB16
TRST
PB15
RS_EN1
PB14
PC4
PC5
PC6
GND
RS_EN2
SHIFT_C
GND
HSYNC
VSYNC
MPC821FADS-DB USER'S MANUAL
DESCRIPTION
I/O, X
Port A Bit 1. Also appears at P8, but is
otherwise unused.
—
—
Not connected.
I/O, X
Port A Bit 0. Also appears at P8, but is
otherwise unused.
—
I/O, X
JTAG Port Test Mode Select signal. It is used
to select testing through the JTAG port. Pulled
up, but is otherwise unused on this board.
I/O, X
Port B Bit 16. Also appears at P8, but is
otherwise unused.
O, L
JTAG Port Reset signal. Pulled down with a
zero ohm resistor so that the JTAG logic is
constantly reset. Otherwise, it is unused on this
board.
I/O, X
Port B Bit 15. Also appears at P8, but is
otherwise unused.
O, L
RS-232 Port 1 Enable signal. It is connected to
the BCSR1.
I/O, X
Port B Bit 14. Also appears at P8, but is
otherwise unused.
I/O, X
Port C Bit 4. Also appears at P8, but is
otherwise unused.
I/O, X
Port C Bit 5. Also appears at P8, but is
otherwise unused.
I/O, X
Port C Bit 6. Also appears at P8, but is
otherwise unused.
—
O, L
RS-232 Port 2 Enable signal. It is connected to
the BCSR1.
I/O, X
Shift Clock signal. PD3/SHIFT/CLK on the
MPC821. Not used on the MPC8xxFADS
motherboard. Also appears at P8 and a
dedicated LCD connector.
—
I/O, X
Horizontal Sync signal. PD4/LOAD/HSYNC on
the MPC821. Not used on the MPC8xxFADS
motherboard. Also appears at P8 and a
dedicated LCD connector.
I/O, X
Vertical Sync signal. PD5/FRAME/VSYNC on
the MPC821. Not used on the MPC8xxFADS
motherboard. Also appears at P8 and a
dedicated LCD connector.
Signal Descriptions
5-27
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