Motorola MPC821FADS User Manual page 35

Table 5-10. PM2 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
86 RSTCNF
87 GND
88 R_PORI
89
GND
90
91
92 BWAITA
93 GND
94 BWP
95 GND
96 BVS1
97 GND
98 BRDY
99
GND
100
101
102 DP3
103 GND
104 BVS2
105 GND
106 BCD1
107 GND
MOTOROLA
DAUGHTERBOARD INPUT/
SIGNAL OUTPUT
RSTCNF
GND
R_PORI
GND
BWAITA
GND
BWP
GND
BVS1
GND
BRDY
GND
DP3
GND
BVS2
GND
BCD1
GND
MPC821FADS-DB USER'S MANUAL
DESCRIPTION
O, L Hard Reset Configuration signal. It is driven
during hard reset to the daughterboard to tell
the MPC821 that it should sample hard reset
configuration from the data bus.
—
O, L Main battery power-on reset signal. Generated
when the main 3.3V bus goes through
power-up or power-down. Drives onboard logic
as well hard reset or power-on reset to the
MPC821.
—
O, L Buffered Wait signal for PCMCIA slot A. Used
to prolong cycles to slow PC cards.
—
O, H Buffered Write-Protect signal for PCMCIA slot
A. IP_A2/IOIS16A on the MPC821. Used as
PC card write-protect indication or as 16-bit I/O
capability indication for PCMCIA slot A.
—
O,X Buffered Voltage Sense 1 signal for PCMCIA
slot A. IP_A0 on the MPC821. Used in
conjunction with BVS2 to determine the
operation voltage of a PCMCIA card.
—
O, H Buffered Ready signal for PCMCIA slot A.
IP_A7 on the MPC821. Used as PCMCIA port
A card ready indication.
—
I/O, X Data Parity line 3. DP3/IRQ6 on the MPC821.
This signal can generate and receive parity
data for the D[24:31] bits that are connected to
the DRAM SIMM. It may also be configured as
IRQ6 signal for the MPC821.
—
O, X Buffered Voltage Sense 2 signal for PCMCIA
slot A. IP_A1 on the MPC821. Used in
conjunction with BVS1 to determine the
operation voltage of a PCMCIA card.
—
O, L Buffered Card Detect 1 signal for PCMCIA slot
A. IP_A4 on the MPC821. Used as a card
detect indication in conjunction with BCD2.
—
Signal Descriptions
5-21