Motorola MPC821FADS User Manual page 33

Table 5-10. PM2 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
38 VFLS1
39
GND
40
41
42 VF1
43 GND
44 AT1
45 GND
46 AT0
47 GND
48 POE_A
49
GND
50
51
52 BADDR30
53 GND
54 ALE_A
55 GND
56 BADDR29
57 GND
58 AS
59 GND
MOTOROLA
DAUGHTERBOARD INPUT/
SIGNAL OUTPUT
VFLS1
GND
VF1
GND
AT1
GND
AT0
GND
POE_A
GND
BADDR30
GND
ALE_A
GND
BADDR29
GND
AS
GND
MPC821FADS-DB USER'S MANUAL
DESCRIPTION
I/O Visible History Flushes Status 1 signal. IP_B1/
IWP1/VFLS1 on the MPC821. In conjunction
with VFLS0, this signal indicates the number of
instructions flushed from the core's history
buffer. It also indicates whether the MPC821 is
in debug mode. If you are not using the debug
port, this signal can be configured for another
function.
—
— Visible Instruction Queue Flushes Status 1
signal. IP_B5/LWP1/VF1 on the MPC821. This
signal can be configured to another function if
you are not using it on the MPC8xxFADS.
—
— Address Type 1 signal. ALE_B/DSCK/AT1 on
the MPC821. Not used on this board. May be
configured for another function.
—
I Address Type 0 signal. IP_B6/DSDI/AT0 on
the MPC821.
—
I, L PCMCIA Buffers Output Enable signal. The
OP1 signal of the PCMCIA interface. Enables
address buffers towards the PC card.
—
I/O,X Burst Address line 30. Dedicated for external
master support. Used to generate a burst
address during external master burst cycles.
Pulled up, but otherwise unused on this board.
—
I, H Address Latch Enable signal for PCMCIA Slot
A. Latches the address in external latches at
the beginning of an access to a PC card.
—
I/O,X Burst Address line 29. Dedicated for external
master support. Used to generate a burst
address during external master burst cycles.
Pulled up, but otherwise unused on this board.
—
I/O, L Address Strobe signal. When asserted by the
external master, the MPC821 recognizes that
an asynchronous cycle is in progress. Pulled
up, but otherwise unused on this board.
—
Signal Descriptions
5-19