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Signal Descriptions
Table 5-10. PM2 Interconnect Signals (Continued)
PIN
MOTHERBOARD
SIGNAL
108
MODIN
109
GND
110
BBVD1
111
GND
112
BCD2
113
GND
114
BBVD2
115
GND
116
117
—
118
DP0
119
V3.3
120
DP2
121
V3.3
122
DP1
123
V3.3
124
—
125
V3.3
126
IRQ1
127
V3.3
128
SPARE3
129
V3.3
5-22
DAUGHTERBOARD
INPUT/
SIGNAL
OUTPUT
MODIN
GND
BBVD1
GND
BCD2
GND
BBVD2
GND
—
DP0
V3.3
DP2
V3.3
DP1
V3.3
—
V3.3
IRQ1
V3.3
SPARE3
V3.3
MPC821FADS-DB USER'S MANUAL
DESCRIPTION
O, X
Mode Clock In signal. This signal selects the
4MHz clock generator or the 32768Hz crystal
as clock sources for the MPC821. Its is driven
by the DS2/4 signal.
—
O, X
Buffered Battery Voltage Detect 1 signal for
PCMCIA slot A. IP_A6 on the MPC821. Used
in conjunction with BBVD2 to determine the
battery status of a PC card.
—
O, L
Buffered Card Detect 2 signal for PCMCIA slot
A. IP_A3 on the MPC823. Used as a card
detect indication in conjunction with BCD1.
—
O, X
Buffered Battery Voltage Detect 2 signal
PCMCIA slot A. IP_A5 on the MPC821. Used
in conjunction with BBVD1 to determine the
battery status of a PC card.
—
—
Not connected.
I/O
Data Parity line 0. DP0/IRQ3 on the MPC821.
This signal can generate and receive parity
data for the D[0:7] signals that are connected to
the DRAM SIMM. It may not be configured as
IRQ3.
—
I/O
Data Parity line 2. DP2/IRQ5 on the MPC821.
This signal can generate and receive parity
data for the D[16:23] signals that are
connected to the DRAM SIMM. It may not be
configured as IRQ5.
—
I/O
Data Parity line1. DP1/IRQ4 on the MPC821.
This signal can generate and receive parity
data for the D[8:15] signals that are connected
to the DRAM SIMM. It may not be configured
as IRQ4.
—
—
Not connected.
—
I/O, L
Interrupt Request line 1.Pulled up, but
otherwise unused on this board.
—
I/O, X
Spare line 3. Pulled up, but otherwise unused
on this board.
—
MOTOROLA
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