Dual-Core Intel® Xeon® Processor E5200 Series Load Current Versus Time; Dual-Core Intel® Xeon® Processor X5200 Series Load Current Versus Time - Intel E5205 - Cpu Xeon 1.86Ghz Fsb1066Mhz 6M Lga771 Dual Core Tray Datasheet

10. This specification refers to the total reduction of the load line due to VID transitions below the specified
VID.
11. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
frequency may have different VID settings.
12. This specification applies to the VCCPLL land.
13. Baseboard bandwidth is limited to 20 MHz.
14. I
CC_TDC
should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal
excursion. Please see the applicable design guidelines for further details. The processor is capable of
drawing I
over various time durations. This parameter is based on design characterization and is not tested.
15. This is the maximum total current drawn from the V
specification does not include the current coming from on-board termination (R
Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine
the total I
16. I
_
CC VTT
17. I
CC_RESET
.
Figure 2-2. Dual-Core Intel® Xeon® Processor E5200 Series Load Current versus Time
Notes:
1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
CC_TDC
2. Not 100% tested. Specified by design characterization.
Figure 2-3. Dual-Core Intel® Xeon® Processor X5200 Series Load Current versus Time
Notes:
1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
CC_TDC
2. Not 100% tested. Specified by design characterization.
30
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications
is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and
indefinitely. Refer to
CC_TDC
drawn by the system. This parameter is based on design characterization and is not tested.
TT
is specified at 1.1 V.
_
OUT
is specified while PWRGOOD and RESET# are asserted.
8 0
75
70
6 5
6 0
55
50
0 . 0 1 0 .1
.
10 0
9 5
9 0
8 5
8 0
75
70
6 5
6 0
0 . 0 1 0 . 1
.
Figure 2-1 for further details on the average processor current draw
plane by only one processor with R
TT
1 10
Tim e Duration (s)
1 10
Tim e Duration (s)
enabled. This
TT
), through the signal line.
TT
10 0 10 0 0
10 0 10 0 0