Timer 1/A Control Register (Tacon) - Samsung S3C8275X User Manual

TIMER 1
Timer 1 Control Register (TACON)
You use the timer 1 control register, TACON, to
•
Enable the timer 1 operating (interval timer)
•
Select the timer 1 input clock frequency
•
Clear the timer 1 counter, TACNT and TBCNT
•
Enable the timer 1 interrupt
•
Clear timer 1 interrupt pending conditions
TACON is located in set 1, bank 1, at address E6H, and is read/write addressable using Register addressing
mode.
A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency
of fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during the normal
operation by writing a "1" to TACON.3.
To enable the timer 1 interrupt (IRQ 0, vector F0H), you must write TACON.7, TACON.2, and TACON.1 to "1".
To generate the exact time interval, you should write TACON.3 and TACON.0 to "10B", which cleared counter
and interrupt pending bit. When the T1INT sub-routine is serviced, the pending condition must be cleared by
software by writing a "0" to the timer 1 interrupt pending bit, TACON.0.
MSB
Timer 1 operating mode selection bit:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)
Timer 1 clock selection bits:
000 = fxx/512
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = fxt (sub clock)
110 = T1CLK (external clock)
111 = Not available
11-2

Timer 1/A Control Register (TACON)

E6H, Set 1, Bank 1, R/W
.7 .6 .5 .4
Figure 11-1. Timer 1/A Control Register (TACON)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
.3 .2 .1 .0
Timer 1 interrupt pending bit:
0 = No interrupt pending (when read)
Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
Timer 1 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 counter operating enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 1 counter clear bit:
0 = No affect
1 = Clear the timer 1 counter (when write)
LSB