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CONTROL REGISTERS
TBCON
— Timer B Control Register
Bit Identifier
Reset Value
Read/Write
Addressing Mode
.7
.6–.4
.3
.2
.1
.0
4-46
.7
.6
–
0
–
R/W
Register addressing mode only
Not used for the S3C8275X/C8278X/C8274X
Timer B Clock Selection Bits
0
0
0
fxx/512
0
0
1
fxx/256
0
1
0
fxx/64
0
1
1
fxx/8
1
0
0
fxt (sub clock)
Others
Not available
Timer B Counter Clear Bit
0
No effect
1
Clear the timer B counter (when write, automatically cleared to "0" after being
cleared basic timer counter)
Timer B Counter Operating Enable Bit
0
Disable counting operation
1
Enable counting operation
Timer B Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer B Interrupt Pending Bit
0
No interrupt pending (when read), clear pending bit (when write)
1
Interrupt is pending (when read)
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
.5
.4
0
0
R/W
R/W
R/W
E7H
Set 1, Bank 1
.3
.2
.1
0
0
0
R/W
R/W
.0
0
R/W
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