S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
Figure 9-5. External Interrupt Control Register, Low Byte (EXTICONL)
Port 0 Pull-up Control Register (P0PUR)
E6H, Set 1, Bank 0, R/W
MSB
.7
.6
P0.7
P0.6
P0.5
P0PUR bit configuration settings:
0
Disable pull-up resistor
1
Enable pull-up resistor
NOTE: A pull-up resistor of port 0 is automatically disabled when the
corresponding pin is selected as push-pull output or alternative
function.
Figure 9-4. Port 0 Pull-up Control Register (P0PUR)
External Interrupt Control Register, Low Byte (EXTICONL)
E9H, Set 1, Bank 0, R/W
MSB
.7
.6
P1.3/INT3
EXTICONL bit configuration settings:
00
Disable interrupt
01
Enable interrupt by falling edge
10
Enable interrupt by rising edge
11
Enable interrupt by both falling and rising edge
.5
.4
.3
.2
P0.4
P0.3
P0.2
.5
.4
.3
.2
P0.2/INT2
P0.1/INT1
.1
.0
LSB
P0.1
P0.0
.1
.0
LSB
P0.0/INT0
I/O PORTS
9-5