Tm Test Under Mask - Samsung S3C8275X User Manual

S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
TM
— Test Under Mask
TM dst,src
Operation: dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags: C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
opc
opc
opc
Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H =
02H, and register 02H = 23H:
TM
TM
TM
TM
TM
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.
dst | src
src dst
dst src
→
R0,R1 R0 = 0C7H, R1 = 02H, Z = "0"
→
R0,@R1 R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
→
00H,01H Register 00H = 2BH, register 01H = 02H, Z = "0"
00H,@01H →
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
→
00H,#54H Register 00H = 2BH, Z = "1"
Bytes Cycles Opcode
2 4
6
3 6
6
3 6
INSTRUCTION SET
Addr Mode
(Hex) dst src
72 r r
73 r lr
74 R R
75 R IR
76 R IM
6-85