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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP System Control and
Interrupts Reference Guide (literature number SPRU712).
3.6
System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes.
discussed.
28x
CPU
A.
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Copyright © 2003–2012, Texas Instruments Incorporated
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Figure 3-9
shows the various clock and reset domains in the 280x devices that will be
Reset
SYSCLKOUT
Peripheral Reset
(A)
CLKIN
Peripheral
CPU
Registers
Timers
System
Clock Enables
Control
Registers
Peripheral
ePWM 1/2/3/4/5/6
Registers
eCAP 1/2/3/4 eQEP 1/2
Peripheral
Registers
Low-Speed Prescaler
Peripheral
Low-Speed Peripherals
Registers
SCI-A/B, SPI-A/B/C/D
High-Speed Prescaler
HSPCLK
ADC
Registers
Figure 3-9. Clock and Reset Domains
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TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230N – OCTOBER 2003 – REVISED MAY 2012
Watchdog
(A)
PLL
Power
Modes
Control
I/O
eCAN-A/B
I/O
I2C-A
LSPCLK
I/O
12-Bit ADC
XRS
Block
X1
OSC
X2
XCLKIN
GPIO
GPIOs
MUX
16 ADC Inputs
Functional Overview
45
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