10.4.3
Serial Status and Data Register (SSD)
The serial status and data register (SSD) is used to set and monitor transmit/receive
operation and error status.
I Serial status and rate register (SSD)
Address
Bit 7
0022
RDRF
H
R
R/W : Readable and writable
: Read-only
R
: Unused
X
: Indeterminate
—
: Initial value
Figure 10.4-4 Serial status and data register (SSD)
Bit 6
Bit 5
Bit 4
Bit 3
ORFE
TDRE
TIE
RIE
R
R
R/W
R/W
Bit 2
Bit 1
Bit 0
Initial value
TD8/TP RD8/RP
00100-1X
R/W
R
RD8/RP
Received data parity selection bit
0
1
TD8/TP
Transmitted data parity selection bit
0
1
RIE
Receiver interrupt enable bit
0
1
TIE
Transmitter interrupt enable bit
0
1
TDRE
Transmission data register empty bit
0
Full of transmission data
1
Receive data flag bit/Error flag bit
RDRF ORFE
0
0
0
1
(When new data is received at
this state, RDRF will not be set)
1
0
Overrun error (Previous data
1
1
CHAPTER 10 UART
B
Odd parity
Even parity
Odd parity
Even parity
Disables interrupt
Enables interrupt
Disables interrupt
Enables interrupt
Empty
No data
Framing error
Normal data
remains)
209