Serial Mode Register (Smr) - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

CHAPTER 9 8-BIT SERIAL I/O
9.3.1

Serial Mode Register (SMR)

The serial mode register (SMR) is used to enable or disable operation, select the shift
clock, set the transfer direction, control interrupts, and check the state of 8-bit serial
I/O.
I Serial mode register (SMR)
Address Bit 7
001C SIOF
H
R/W
R/W : Readable and writable
: Initial value
176
Figure 9.3-3 Serial mode register (SMR)
Bit 6 Bit 5 Bit 4 Bit 3
SIOE SCKE SOE CKS1
R/W R/W R/W R/W
Bit 2 Bit 1 Bit 0 Initial value
CKS0 BDS SST 00000000
R/W R/W R/W
Serial I/O transfer start bit
SST
Read
0 Serial transfer stopped.
1 Serial transfer operating.
BDS
Transfer direction selection bit
0 LSB first (starts transfer from the least significant bit)
1 MSB first (starts transfer from the most significant bit)
CKS1 CKS0 Shift cl ock sel ecti on bits
0 0
Internal shift
0 1
clock
1 0
1 1 External shift clock
t : Instruction cycle
inst
Serial data output enable bit
SOE
0 Functions P44/SO as the general-purpose I/O port
1 Functions P44/SO as the serial data output pin.
Shift clock output enable bit
SCKE
Functions P45/SCK as a general-purpose I/O port
0
or shift clock input pin.
1 Functions P45/SCK as the shift clock output pin.
Interrupt request enable bit
SIOE
0 Disables interrupt request output.
1 Enables interrupt request output.
Interrupt request flag bit
SIOF
Read
Transfer has not
0
completed.
Transfer has completed. No effect.The bit does not
1
B
Write
Stops/disables serial
transfer.
Starts/enables serial
transfer.
SCK p in
2 t Output
inst
8 t Output
inst
32 t Output
inst
Input
.
Write
Clears this bit.
change