Operating States In Standby Mode - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

CHAPTER 3 CPU
3.7.1

Operating States in Standby Mode

This section describes the operating states of the CPU and peripheral functions in
standby mode.
I Operating states during standby mode
Table 3.7-1 Operating states of the CPU and peripheral functions in standby mode
Function
Main clock
Instructions
CPU ROM
RAM
I/O ports
Timebase timer
8-bit PWM timer
8-bit PWC timer
Peripheral
Watchdog timer
functions
LCD controller/driver
External Interrupts
Serial I/O
UART
*1: If pull-up is selected, it will be "H" level.
G
Pin States in Standby Mode
Almost all I/O pins will either keep the state they were placed in, or go to the high-impedance state
according to the pin state control bit of the standby control register (STBC: SPL) just prior to going to the
stop mode. This is true regardless of the clock mode.
See Appendix E "MB89950/950A Series Pin States" for pin states in standby mode.
58
Main clock mode
Run Sleep
Operating Operating
Operating Stop
Operating Hold
Operating Hold
Operating Operating
Operating Operating
Operating Operating
Operating Stop
Operating Operating
Operating Operating
Operating Operating
Operating Operating
Stop Stop
(SPL = "0") (SPL = "1")
Stop Stop
Stop Stop
Hold Hold
Hold
Hi-Z
Stop Stop
Stop Stop
Stop Stop
Stop Stop
Stop Stop
Operating Operating
Stop Stop
Stop Stop
(*1)