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CHAPTER 3 CPU
I Memory access mode selection operation
Only the single-chip mode can be selected.
Table 3.8-2 "Mode pin and mode data" lists the mode pin and mode data options.
Table 3.8-2 Mode pins and mode data
Memory access mode
Single-chip mode
Other modes
Figure 3.8-2 "Memory access selection operation" shows the operation for memory access mode selection.
Check mode pin
Delay for wake-up from
reset source
(external reset or
oscillation stabilization
delay time)
Mode fetch
Check mode data
Set I/O pin functions
for program
execution (RUN)
68
Mode pin (MODA)
Figure 3.8-2 Memory access selection operation
Prohibited
setting
Prohibited
setting
V
SS
Prohibited settings
Reset source generated
Other
Mode pin (MODA)
Read mode data from
internal ROM
Reset active?
Fetch mode data and reset
vector from internal ROM.
Other
Mode data
Set I/O pins to input or output
depending on their respective port
data direction registers (DDR),
etc.
Mode data
00
H
Prohibited settings
V
SS
Single-chip mode
I/O pins are high
impedance
Single-chip mode (00
)
H
I/O pins are available as
ports
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