Timebase Timer Control Register (Tbtc) - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

CHAPTER 5 TIMEBASE TIMER
5.3

Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) is used to select the interval times bit, clear
the counter, control interrupts, and check the state of the timebase timer.
I Timebase timer control register (TBTC)
Address Bit 7
000A
H
R/W :Readable and writable
W :Write-only
— : Unused
: Initial value
104
Figure 5.3-1 Timebase timer control register (TBTC)
Bit 6 Bit 5 Bit 4 Bit 3
TBIF TBIE
R/W R/W
Bit 2 Bit 1 Bit 0
TBR TBC1 TBC0
W R/W R/W
TBC1 TBC0 Interval time selection bits
0 0
0 1
1 0
1 1
F : Main clock oscillation frequency
CH
Timebase timer initialization bit
TBR
Read
0 —
Reading always returns
1
"1".
TBIE Interrupt request enable bit
0 Disables interrupt request output.
1 Enables interrupt output.
Overflow interrupt request flag bit
TBIF
Read
No overflow on specified
0
bit.
1 Overflow on specified bit.
Initial value
---00000
B
15
2 /F
CH
2 17 /F
CH
2 19 /F
CH
2 21 /F
CH
Write
Clears timebase timer
counter
No effect. The bit does
not change.
Write
Clears this bit.
No effect. The bit does
not change.