Pci Interrupt Routing Map - Intel D810E2CA3 Specification

2.7 PCI Interrupt Routing Map

This section describes interrupt sharing and how the interrupt signals are connected between the
PCI expansion slots and onboard PCI devices. The PCI specification specifies how interrupts can
be shared between devices attached to the PCI bus. In most cases, the small amount of latency
added by interrupt sharing does not affect the operation or throughput of the devices. In some
special cases where maximum performance is needed from a device, a PCI device should not share
an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt
with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
INTA: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is
classified as INTB. (This is not an absolute requirement.)
INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
The ICH2 has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt
sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some PCI
interrupt sources are electrically tied together on the D810E2CA3 board and therefore share the
same interrupt. Table 18 shows an example of how the PIRQ signals are routed on the
D810E2CA3 board. For example, using Table 18 as a reference, assume an add-in card using
INTA is plugged into PCI bus connector 4. In PCI bus connector 4, INTA is connected to PIRQB,
which is already connected to the SMBus. The add-in card in PCI bus connector 4 now shares
interrupts with these onboard interrupt sources.
Table 18.

PCI Interrupt Routing Map

PCI Interrupt Source
GMCH
ICH2 USB controller #1
SMBus controller
ICH2 USB controller #2
ICH2 Audio
ICH2 LAN
PCI Bus Connector 1 (J3D1)
PCI Bus Connector 2 (J3C1)
PCI Bus Connector 3 (J3B1)
PCI Bus Connector 4 (J3A2)
NOTE
The ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 7, 9, 10, 11, 14,
and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt.
However, in certain interrupt-constrained situations, it is possible for two or more of the
PIRQ lines to be connected to the same IRQ signal.
ICH PIRQ Signal Name
PIRQF PIRQG PIRQC
INTB INTC INTA
INTA INTB INTD
INTD INTA INTC
INTC INTD INTB
Technical Reference
PIRQB Other
INTB INTA to PIRQA
INTD to PIRQD
INTB
INTC to PIRQH
INTB
INTA to PIRQE
INTD
INTC
INTB
INTA
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