Pci Bus Connectors (J3A2, J3B1, J3C1, J3D1) - Intel D810E2CA3 Specification

Intel Desktop Board D810E2CA3 Technical Product Specification
Table 37.

PCI Bus Connectors (J3A2, J3B1, J3C1, J3D1)

Pin Signal
A1 Ground (TRST#)
(Note 1)
A2 +12 V
A3 +5 V (TMS)
(Note 1)
A4 +5 V (TDI)
(Note 1)
A5 +5 V
A6 INTA#
A7 INTC#
A8 +5 V
A9 Reserved
A10 +5 V (I/O)
A11 Reserved
A12 Ground
A13 Ground
A14 +3.3 V aux
A15 RST#
A16 +5 V (I/O)
A17 GNT#
A18 Ground
A19 PME#
A20 AD30
A21 +3.3 V
A22 AD28
A23 AD26
A24 Ground
A25 AD24
A26 IDSEL
A27 +3.3 V
A28 AD22
A29 AD20
A30 Ground
A31 AD18
Notes:
1. These signals (in parentheses) are optional in the PCI specification and are not currently implemented.
2. On PCI bus connector 2, this pin is connected to the optional SMBus clock line.
3. On PCI bus connector 2, this pin is connected to the optional SMBus data line.
60
Pin Signal
B1 -12 V
(Note 1)
B2 Ground (TCK)
B3 Ground
B4 Not connect ed (TDO)
(Note 1)
B5 +5 V
B6 +5 V
B7 INTB#
B8 INTD#
B9 Not connected
(Note 1)
(PRSNT1#)
B10 Reserved
B11 Not connected
(Note 1)
(PRSNT2#)
B12 Ground
B13 Ground
B14 Reserved
B15 Ground
B16 CLK
B17 Ground
B18 REQ#
B19 +5 V (I/O)
B20 AD31
B21 AD29
B22 Ground
B23 AD27
B24 AD25
B25 +3.3 V
B26 C/BE3#
B27 AD23
B28 Ground
B29 AD21
B30 AD19
B31 +3.3 V
Pin Signal Pin
A32 AD16 B32
A33 +3.3 V B33
A34 FRAME# B34
A35 Ground B35
A36 TRDY# B36
A37 Ground B37
A38 STOP# B38
A39 +3.3 V B39
A40 Reserved B40
(Note 2)
A41 Reserved B41
(Note 3)
A42 Ground B42
A43 PAR B43
A44 AD15 B44
A45 +3.3 V B45
A46 AD13 B46
A47 AD11 B47
A48 Ground B48
A49 AD09 B49
A50 Key B50
A51 Key B51
A52 C/BE0# B52
A53 +3.3 V B53
A54 AD06 B54
A55 AD04 B55
A56 Ground B56
A57 AD02 B57
A58 AD00 B58
A59 +5 V (I/O) B59
A60 REQ64C# B60
A61 +5 V B61
A62 +5 V B62
Signal
AD17
C/BE2#
Ground
IRDY#
+3.3 V
DEVSEL#
Ground
LOCK#
PERR#
+3.3 V
SERR#
+3.3 V
C/BE1#
AD14
Ground
AD12
AD10
Ground
Key
Key
AD08
AD07
+3.3 V
AD05
AD03
Ground
AD01
+5 V (I/O)
ACK64C#
+5 V
+5 V