Bus Initialization Checkpoints; Upper Nibble High Byte Functions - Intel D810E2CA3 Specification

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Table 77.
Runtime Code Uncompressed in F000 Shadow RAM (continued)
Code
Description of POST Operation
AD
Put CGA INT10 module, if present, in shadow RAM.
AE
Uncompress SMBIOS module, initialize SMBIOS code, and form the runtime SMBIOS image in
shadow RAM.
B1
Ready to copy any code to specific area.
00
Copying of code to specific area complete. Ready to give control to INT19 boot loader.

5.3 Bus Initialization Checkpoints

The system BIOS gives control to the different buses at the following checkpoints to do various
tasks. Table 78 describes the bus initialization checkpoints.
Table 78.

Bus Initialization Checkpoints

Checkpoint
Description
2A
Different buses init (system, static, output devices) to start, if present.
38
Different buses init (input, IPL, general devices) to start, if present.
39
Display different buses initialization error messages.
95
Initialization of different buses optional ROMs from C800 to start.
While control is inside the different bus routines, additional checkpoints are output to port 80h as
word values to identify the routines under execution. In these word-value checkpoints, the low
byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the
different bus routines. The high byte of the checkpoint is the indication of which routine is being
executed in the different buses. Table 79 describes the upper nibble of the high byte and indicates
the function being executed.
Table 79.

Upper Nibble High Byte Functions

Value
Description
0
func#0, disable all devices on this bus
1
func#1, initialize static devices on this bus
2
func#2, initialize output device on this bus
3
func#3, initialize input device on this bus
4
func#4, initialize IPL device on this bus
5
func#5, initialize general device on this bus
6
func#6, report errors on this bus
7
func#7, initialize add-on ROM on all buses
Error Messages and Beep Codes
109

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