Bsp Identification; Boot Control Support; Post Code Display - Intel X38ML - Server Board Motherboard Technical Manual

Intel® Server Board X38ML
After the BIOS identifies and saves the BSP information, it sets the FRB2 timer use bit and
loads the watchdog timer with the new timeout interval.
If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so
configured) logs a watchdog expiration event showing the FRB2 timeout in the event data bytes.
The BMC then hard resets the system, assuming the selected BIOS resets as the watchdog
timeout action.
The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan
and before displaying a request for a boot password. If the processor fails and causes an FRB2
time-out, the BMC resets the system.
The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired
FRB2 timer, the BIOS enters the failure in the system event log (SEL). In the OEM bytes entry
in the SEL, the last POST code generated during the previous boot attempt is written. An FRB2
failure is not reflected in the processor status sensor value.
The FRB2 failure does not affect the front panel LEDs.
5.6.2.1 Watchdog Timer Timeout Reason Bits
To implement FRB2, the BIOS determines during POST if a BMC watchdog timer timeout
occurred on the previous boot attempt. If it finds a watchdog timeout did occur, it determines
whether that timeout was an FRB2 timeout, a system management software (SMS) timeout, or
an intentional, timed hard reset. The BMC provides the IPMI Get Watchdog Timer command to
facilitate determining the cause of watchdog time out.
The BMC maintains the timeout-reason bits across system resets and DC power cycles, but not
across AC power cycles.
5.6.3

BSP Identification

The BMC cannot indicate which processor is the BSP. You can use software to identify the
BSP, as long as it uses the multiprocessor specification tables. See the BIOS EPS for additional
details.
5.6.4

Boot Control Support

The BMC supports the IPMI 2.0 boot control feature that allows the boot device and boot
parameters to be managed remotely.
5.6.5

Post Code Display

When the Integrated BMC receives standby power, it initializes internal hardware to monitor port
80h (POST code) writes. Data written to port 80h is output to the system POST LEDs. Note that
although the port 80h data is ready by a hardware FIFO, output to the LEDs is driven by
firmware. This could lead to delays between the write and subsequent display on the LEDs.
There is also no flow control for port 80h writes, so a burst of data could result in the old POST
codes being dropped from the FIFO before they display on the LEDs.
Revision 1.3
Intel order number E15331-006
Platform Management
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