Error Reporting; Error Sources And Types; Pci Bus Errors; Intel® Pentium® Iii Processor Bus Errors - Intel SDS2 Specification

Server Management
Function Voltage
CSB5 3.3 V
DIMM 1 3.3 V
DIMM 2 3.3 V
DIMM 3 3.3 V
DIMM 4 3.3 V
DIMM 5 3.3 V
DIMM 6 3.3 V
PCK2001M 3.3 V
Function Voltage
NIC1 3 VSB
NIC2 3VSB
5.4

Error Reporting

This section documents the types of system bus error conditions monitored by the SDS2 Server
Board.
5.4.1

Error Sources and Types

One of the major requirements of server management is to correctly and consistently handles
system errors. System errors on the SDS2, which can be disabled and enabled individually, can
be categorized as follows:
PCI bus
Processor bus errors
Memory single- and multi-bit errors
General server management sensors, managed by the Sahalee BMC
5.4.2

PCI Bus Errors

The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI-related errors are reported by
SERR#. SERR# is routed to NMI if enabled by BIOS.
5.4.3 Intel® Pentium® III Processor Bus Errors
The HE-SL supports all the data integrity features supported by the Pentium Pro bus including
Address, Request and Response parity. The HE-SL always generates ECC data while it is driving
the processor data bus although data bus ECC can be disabled or enabled by BIOS (enabled by
default). The HE-SL generates MIRQ# on SBEs (Single-bit errors) and generates SALERT# on
32
Address
0xC2 South Bridge
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
0xD2 Clock Buffers
Table 21. Private I
Address
0x84
0x86
Order Number: A85874-002
Notes
2
C Bus 4 Devices
Notes
Intel® Server Board SDS2
Revision 1.2