Intel CORE 2 DUO E4000 - DATASHEET 3-2008 Datasheet page 21
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Electrical Specifications
Table 5.
Voltage and Current Specifications
Symbol
V
PLL V
CCPLL
Processor Number
I
CC
Processor Number
FSB termination voltage
V
TT
(DC + AC specifications)
DC Current that may be drawn from
VTT_OUT_LEFT and
VTT_OUT_LEFT and VTT_OUT_RIGHT per
VTT_OUT_RIGHT I
CC
pin
I
CC
I
TT
I
CC
I
I
CC_VCCPLL
CC
I
I
CC_GTLREF
CC
NOTES:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
These specifications will be updated with characterized data from silicon measurements at a later date.
2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such
that two processors at the same frequency may have different settings within the VID range. Note this differs
from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel
®
SpeedStep
Technology, or Extended HALT State).
4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different
voltage is required. See
5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket
with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system
is not coupled into the oscilloscope probe.
6. Refer to
Table 6
and
Figure 1
processor should not be subjected to any V
current.
7. I
specification is based on the V
CC_MAX
8. V
must be provided via a separate voltage source and not be connected to V
TT
at the land.
9. Baseboard bandwidth is limited to 20 MHz.
10.This is maximum total current drawn from V
the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0
Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total I
system. This parameter is based on design characterization and is not tested.
Datasheet
Parameter
CC
I
for
CC
775_VR_CONFIG_06
E6850
3.00 GHz
E6750
2.66 GHz
E6700
2.66 GHz
E6600
2.40 GHz
E6550
2.33 GHz
E6540
2.33 GHz
E6400/E6420
2.13 GHz
E6300/E6320
1.86 GHz
E4700
2.60 GHz
E4600
2.40 GHz
E4500
2.20 GHz
E4400
2.00 GHz
E4300
1.80 GHz
I
for
CC
775_VR_CONFIG_05B
X6800
2.93 GHz
for V
supply before V
TT
CC
for V
supply after V
stable
TT
CC
for PLL land
for GTLREF
Section 2.3
and
Table 2
for more information.
for the minimum, typical, and maximum V
and I
CC
loadline. Refer to
CC_MAX
plane by only the processor. This specification does not include
TT
Min
Typ
- 5%
1.50
—
—
1.14
1.20
—
stable
—
—
—
allowed for a given current. The
CC
combination wherein V
CC
Figure 1
for details.
Max
Unit
Notes
+ 5%
75
75
75
75
75
—
75
75
A
75
75
75
75
75
75
—
90
1.26
V
—
580
mA
4.5
—
A
4.6
—
130
mA
—
200
μA
exceeds V
for a given
CC
CC_MAX
. This specification is measured
CC
drawn by the
TT
1, 2
7
8
9
10
21
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