Peci Dc Specifications; Peci Dc Electrical Limits - Intel CORE 2 DUO E4000 - DATASHEET 3-2008 Datasheet

Electrical Specifications
2.8

PECI DC Specifications

PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
Table 19.

PECI DC Electrical Limits

Symbol
V
in
V
hysteresis
V
n
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
NOTES:
V supplies the PECI interface. PECI behavior does not affect V
1.
TT
to
Table 4
The input buffers use a Schmitt-triggered input design for improved noise immunity.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
Datasheet
Definition and Conditions
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V = 0.75 * V
OH TT)
Low level output sink
(V = 0.25 * V )
OL TT
High impedance state leakage to V
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above 300 MHz
for V specifications.
TT
Min Max
-0.15 V
0.1 * V —
TT
0.275 * V 0.500 * V
TT
0.550 * V 0.725 * V
TT
-6.0 N/A
0.5 1.0
N/A 50
TT
N/A 10
N/A 10
0.1 * V —
TT
min/max specifications. Refer
TT
§ §
1
Units Notes
V
TT
2
V
V
TT
V
TT
mA
mA
3
µA
3
µA
4
pF
V
p-p
33