Table Of Contents - Intel CORE 2 DUO E4000 - DATASHEET 3-2008 Datasheet

Contents
1 Introduction ............................................................................................................ 11
1.1 Terminology ..................................................................................................... 12
1.1.1 Processor Terminology ............................................................................ 12
1.2 References ....................................................................................................... 14
2 Electrical Specifications ........................................................................................... 15
2.1 Power and Ground Lands.................................................................................... 15
2.2 Decoupling Guidelines ........................................................................................ 15
2.2.1 VCC Decoupling ..................................................................................... 15
2.2.2 Vtt Decoupling ....................................................................................... 15
2.2.3 FSB Decoupling...................................................................................... 16
2.3 Voltage Identification ......................................................................................... 16
2.4 Market Segment Identification (MSID) ................................................................. 18
2.5 Reserved, Unused, and TESTHI Signals ................................................................ 18
2.6 Voltage and Current Specification ........................................................................ 19
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 19
2.6.2 DC Voltage and Current Specification ........................................................ 20
2.6.3 V
CC
2.6.4 Die Voltage Validation ............................................................................. 24
2.7 Signaling Specifications...................................................................................... 25
2.7.1 FSB Signal Groups.................................................................................. 25
2.7.2 CMOS and Open Drain Signals ................................................................. 27
2.7.3 Processor DC Specifications ..................................................................... 27
2.7.3.1
2.7.4 Clock Specifications ................................................................................ 29
2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 29
2.7.6 FSB Frequency Select Signals (BSEL[2:0])................................................. 29
2.7.7 Phase Lock Loop (PLL) and Filter .............................................................. 30
2.7.8 BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
2.7.9 BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
2.8 PECI DC Specifications ....................................................................................... 33
3 Package Mechanical Specifications .......................................................................... 35
3.1 Package Mechanical Drawing............................................................................... 35
3.1.1 Processor Component Keep-Out Zones ...................................................... 39
3.1.2 Package Loading Specifications ................................................................ 39
3.1.3 Package Handling Guidelines.................................................................... 39
3.1.4 Package Insertion Specifications............................................................... 40
3.1.5 Processor Mass Specification .................................................................... 40
3.1.6 Processor Materials................................................................................. 40
3.1.7 Processor Markings................................................................................. 40
3.1.8 Processor Land Coordinates ..................................................................... 43
4 Land Listing and Signal Descriptions ....................................................................... 45
4.1 Processor Land Assignments ............................................................................... 45
4.2 Alphabetical Signals Reference ............................................................................ 68
5 Thermal Specifications and Design Considerations .................................................. 77
5.1 Processor Thermal Specifications ......................................................................... 77
5.1.1 Thermal Specifications ............................................................................ 77
5.1.2 Thermal Metrology ................................................................................. 84
5.2 Processor Thermal Features ................................................................................ 84
5.2.1 Thermal Monitor..................................................................................... 84
5.2.2 Thermal Monitor 2 .................................................................................. 85
5.2.3 On-Demand Mode .................................................................................. 86
Datasheet
Overshoot ....................................................................................... 24
GTL+ Front Side Bus Specifications ............................................. 28
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