Processor 2/7-Clk, Misc - Clevo W340EU Service Manual

Schematic Diagrams
Processor 2/7
PU/PD for JTAG signals
VTT_CPU
Sheet 3 of 42
Processor 2/7-CLK,
MISC
[11,17,23]
B - 4 Processor 2/7- CLK, MISC
- CLK, MISC
Ivy/Sandy Bridge Processor 2/7
R359 *51_04 XDP_TMS
XDP_TDI_R
R89 *51_04
XDP_PREQ#
R90 *51_04
XDP_TDO_R
R358 *51_04
R357 *51_04 XDP_TCLK
R85 51_04 XDP_TRST#
H_SNB_IVB#
[18] H_SNB_IVB#
3.3VS
XDP_DBR_R
R88 *1K_04
12/14
D 04
H_CATERR#
H_PECI_R
R100 *10mil_04
[18,27] H_PECI
H_PROCHOT#_D
R79 56_04
[36] H_PROCHOT#
If PROCHOT# is not used, then it must
be terminated with a 68-£[ +-5%
pull-up resistor to 1.05VS_VTT .
H_THRMTRIP#_R
R107 *10mil_04
[18] H_THRMTRIP#
PM_SY NC_R
R97 *10mil_04
[15] H_PM_SY NC
H_CPUPWRGD_R
R105 *10mil_04
[18] H_CPUPWRGD
PMSY S_PWRGD_BUF R44 130_1%_04 VDDPWRGOOD_R
Buffered reset to CPU
VTT_CPU BUF_CPU_RST#
R93 75_1%_04 R86 43_1%_04
6
3.3VS D
Q15A 12/9
2
R95 10K_04 G MTDK5S6R
S
1
3
D
5 G Q15B
PLT_RST#
S MTDK5S6R
4
D 04
R567 *2K_1%_04
[27]
R568
R96
*100K_04
*1K_1%_04 CAD Note: Capacitor
need to be placed
close to buffer output pin
( CLK,MISC,JTAG )
U34B
A28
BCLK
C26 A27
PROC_SELECT# BCLK#
AN34
SKTOCC#
A16
DPLL_REF_CLK
A15
DPLL_REF_CLK#
AL33
CATERR#
AN33 R8 CPUDRAMRST#
PECI SM_DRAMRST#
AL32 AK1 SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP_1
SM_RCOMP[1]
A4 SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29 XDP_PRDY #
PRDY# AP27
XDP_PREQ#
PREQ#
AR26 XDP_TCLK
TCK
AR27 XDP_TMS
TMS
AM34 AP30 XDP_TRST#
PM_SY NC TRST#
AR28
XDP_TDI_R
TDI AP26
XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35 XDP_DBR_R
V8 DBR#
SM_DRAMPWROK
AT28
XDP_BPM0_R
BPM#[0]
AR29 XDP_BPM1_R
BPM#[1]
AR30 XDP_BPM2_R
BPM#[2]
AR33 AT30 XDP_BPM3_R
RESET# BPM#[3] AP32
XDP_BPM4_R
BPM#[4]
AR31
XDP_BPM5_R
BPM#[5]
AT31 XDP_BPM6_R
BPM#[6]
AR32 XDP_BPM7_R
BPM#[7]
FOXCONN PZ98821-364B-01F
H_PROCHOT#
Q14
G
H_PROCHOT_EC
2SK3018S3 C124
47p_50V_NPO_04
R78 *100K_04
[2,5,6,18,19,20,34,35,36]
[2,6,11,13,14,15,17,18,19,20,22,23,24,26,28,29,31,33,34,35]
[9,10,11,12,13,14,15,16,17,18,19,20,23,24,25,27,28,29,30,31,36]
Processor Pullups/Pull downs
H_PROCHOT#
R84 62_04
H_CPUPWRGD_R R104 10K_04
C139 *0.1u_10V_X5R_04
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
CLK_EXP_P [14]
CLK_EXP_N [14]
SM_RCOMP_0 R354 140_1%_04
CLK_DP_P [14]
SM_RCOMP_1
R349 25.5_1%_04
CLK_DP_N [14]
SM_RCOMP_2 R348 200_1%_04
S3 circuit:- DRAM PWRGOOD logic
1.5V
3.3V
R52 R46
*200_1%_04 200_1%_04
D4
1
A
[15] PM_DRAM_PWRGD
3
C
2
A
[15,33] 1.8VS_PWRGD
*BAT54AS3
R45
*39_04
R47 *10mil_04
Q12
G
[31,33,34] SUSB
*2SK3018S3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R28 *0_04
R29
1K_04
Q8
2SK3018S3
S D
CPUDRAMRST# R30 1K_04
DDR3_DRAMRST#
R27
DRAMRST_CNTRL [9,10,14]
C31
0.047u_10V_X7R_04
VTT_CPU
[6,9,10,20,31,33] 1.5V
3.3V
3.3VS
VTT_CPU
D 04
PMSY S_PWRGD_BUF
[9,10]